Press release from Business Wire India
Source: Sequence Design
Tuesday, July 21, 2009 12:46 PM IST (07:16 AM GMT)
Editors: General: Consumer interest; Business: Advertising, PR & marketing, Business services, Information technology; Technology
Sequence Launches PowerArtist-XP – Industry’s First Automatic, Fully Integrated RTL Design for Power Platform
Delivers High Productivity with Analysis-Driven Power Reduction and Minimal Area Overhead
Sunnyvale, California, United States, Tuesday, July 21, 2009 — (Business Wire India) — Sequence Design, the EDA leader Enabling Design For Power (DFPT), today announced PowerArtist-XP, the first and most comprehensive analysis-driven, automatic RTL power-reduction technology within a completely integrated environment. IP and SoC RTL designers, without becoming power experts, can analyze, visualize and reduce power by 10-60% or more within minutes on multi-million instances, with 50% fewer RTL edits, and productivity gains of 10X at a minimum.
“Power management is a top priority and Sequence’s PowerArtist-XP is a key tool we use for power efficient RTL design flows,” said Jiebing Wang, Vice President of Acceleration Technology at Exar Corporation. “The tool has provided significant power reduction in our designs. PowerArtist-XP also has enabled our RTL designers to become power aware by providing methods to analyze and reduce power early in the design process while being easy to integrate in our design flows.”
PowerArtist-XP – selected as a DAC 2009 “must-see” by famed analyst Gary Smith – will be showcased alongside Sequence’s complete technology lineup at this year’s DAC, Booth 3455. For demo and product information: http://www.sequencedesign.com/newsevents/events.php.
The tool delivers maximum power savings, in minimum time, with the least number of RTL edits. Sequence’s new XPRTT (eXtreme Power Reduction Technology) incorporated here maximizes power savings early at RTL – the highest level of hardware abstraction enabling high productivity. XPRT delivers the industry’s most comprehensive set of RTL power reductions yet – power reduction is not just sequential and combinational clock gating, but is also targeted for memory and datapath portions of complex SoCs and IPs.
Integrating the industry-leading PowerTheater timing-aware power analysis technology, PowerArtist-XP users now benefit from a one-stop shop for RTL power. By predicting power savings and area trade-offs upfront at RTL, single-pass power reduction identifies the highest impact RTL edits. Productivity increases multi-fold by obviating unnecessary iterations with synthesis and implementation while decreasing the impact on area, timing closure, verification, and functional ECOs. The integrated RTL power environment also enables designers to quickly discover power bugs, manage stimulus for peak and average power, generate custom reports for power regressions using the OpenAccess database, and more.
A powerful graphical cockpit, PowerCanvasT, drives power-ordered reductions while providing a wide range of tightly interlinked visual debug diagnostics that make power easy for mainstream RTL designers. PowerArtist-XP automatically generates power-optimized RTL with surgical changes – in addition, the versatile PowerCanvas reduction dialogs provide both flexibility and precise guidance to the RTL designers in making rapid RTL edits.
“PowerArtist has proven itself by giving us the power savings and productivity gains we need,” said Jon Gibbons, Ubicom Vice President of VLSI Engineering. “By raising the bar with PowerArtist-XP, Sequence continues to advance the state of the art in low-power design, and we look forward to working with this exciting new technology.”
“Since we launched PowerArtist at DAC last year, we saw a growing demand from customers for an integrated solution addressing power reduction more intelligently,” said Vic Kulkarni, President & CEO of Sequence. “For sub-65nm designs, an RTL analysis-driven power reduction approach becomes very critical since surgical changes are now possible in order to achieve maximum possible power reduction with minimal area overhead and minimal ECO loops. Power reduction with analysis-driven vs. ‘blind’ automation is the only meaningful approach for designers to lower power and avoid falling in the traps of poor QoR and an excess of ineffective changes.”
PowerArtist-XP is compatible with all standard design flows, including synthesis, simulation, and formal verification, and all leading formats and constraints including Common Power Format (CPF), Unified Power Format (UPF) and Synopsys Design Constraints (SDC). Utilizing Si2’s OpenAccess database (OADB), it uniquely allows users to have detailed access to power information to create custom reports or automate proprietary power reductions through an open Tcl API.
PowerArtist-XP is in production now. North America list pricing starts at $220,000 for a one-year TBL. For more information: www.sequencedesign.com.
Sequence Design – winner of the 2009 IEC DesignVision Award, featured in EDN’s Hot 100 Products for 2008 and SiliconIndia’s Top 5 EDA Companies – is the EDA leader Enabling Design For Power to accelerate the ability of SoC designers to bring high-performance, power-aware ICs to market. Sequence’s power and signal-integrity software give customers the competitive advantage necessary to excel in aggressive technology markets. For more information: sequencedesign.com.
Jim Lochmiller, Sequence Public Relations, (541) 292-0959, [email protected]
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